The entire disclosure of the copending U.S. patent application Ser. No. 09/087,864 filed on Jun. 1, 1998 by the same applicant as the present application is incorporated herein by reference.
1. Field of the Invention
This invention relates to a method of controlling clock signals and to a clock control circuit. More particularly, the invention relates to a clock signal control method and circuit ideal for application to a semiconductor integrated circuit device synchronized to a system clock to control internal circuitry. More specifically, the invention relates to a circuit that uses a timing averaging circuit for clock control, as well as to a clock control circuit that uses a timing averaging circuit in a synchronizing circuit such as a delay-locked loop, phase synchronizing loop or synchronous delay circuit.
2. Description of the Related Art
In a semiconductor integrated circuit synchronized to a system clock to control internal circuitry, the entirety of the internal circuitry is controlled by executing a given circuit operation every cycle of the clock.
In order to assure operation that takes variance due to system clock jitter into account in a semiconductor integrated circuit of this kind, the length of time in clock cycle that can actually be used for circuit operation is obtained by subtracting jitter time from the period of the clock.
Accordingly, if we let Tmin represent the minimum time necessary for circuit operation executed in one clock cycle, then it will be necessary for the minimum period tCKmin of the clock to be set to a time Tmin+Tjitter, namely a length of time obtained by adding jitter time Tjitter to Tmin, as shown in FIG. 16.
Further, in order to reduce delay time between the system clock and an internal clock or to multiply the frequency of the clock in a semiconductor integrated circuit synchronized to a system clock to control the internal circuitry, the conventional practice is to use a phase-locked loop (PLL), a delay-locked loop (DLL) or a synchronous delay circuit. However, these clock control circuits can be a source of clock jitter and are susceptible to jitter of the system clock, in which case locking time is prolonged. Thus, these circuits tend to degrade the synchronization characteristic.
A PLL is effective in reducing jitter depending upon how the PLL is set up. In a PLL, a clock having a frequency and phase the same as those of an external clock is generated by a voltage-controlled oscillator (VCO) 105 configured for feedback, as shown in FIG. 21. In this arrangement, the jitter component of the system clock is suppressed by a phase comparator 102, a charge pump 103 connected to the output of the phase comparator 102 and a loop filter 104 connected to the output of the charge pump 103, thus making it possible to reduce jitter of the clock generated by the VCO 105. The charge pump 103 receives the output (UP and DOWN signals, etc.) from the phase comparator 102 and the output node thereof is charged or discharged, whereby a voltage corresponding to the phase difference between the clock and the output of the VCO 105 is applied as the input voltage of the loop filter 104.
Because a PLL is a feedback circuit, however, a long period of time on the order of several hundred to several thousand cycles is required until the clock stabilizes. In addition, if jitter is too large, there is the possibility that the PLL will not remain locked.
In a DLL, on the other hand, a clock having a phase the same as those of an external clock is generated by a voltage-controlled delay circuit 115 configured for feedback, as shown in FIG. 22. A problem that arises, therefore, is that external clock jitter passes through the delay circuit as is and is transmitted to the internal circuitry from a clockdriver 106.
In a synchronous delay circuit, as shown in FIG. 23, a pair of delay circuit chains 901, 902 and a dummy delay circuit 905, which comprises an input buffer dummy 905A and a clock driver dummy 905B, are used to subtract the delay time (td1+td2) of the dummy delay circuit 905 from the clock period tCK of a clock whose phase is the same as that of an external clock, whereby a delay quantity tV is obtained. The delay quantity tV is measured as the length of time of travel through the delay circuit chain 901, and the delay is reproduced by the other delay circuit chain 902, thereby synchronizing the internal clock to the external clock.
The synchronous delay circuit, which eliminates clock skew in a short synchronization time, finds use in high-speed clock synchronizing circuits thanks to the simplicity of the circuitry and the low power consumption. Reference is had to the following literature which cites examples of synchronous delay circuits of this kind:
[1] The specification of Japanese Patent Application Laid-Open (KOKAI) No. 8-237091;
[2] Jin-Man Han et al., xe2x80x9cSkew Minimization Technique for 256M-bit Synchronous DRAM and beyond.xe2x80x9d 1996 Symp. on VLSI Circ. pp. 192-193;
[3] Richard B. Watson et al., xe2x80x9cClock Buffer Chip with Absolute Delay Regulation Over Process and Environment Variations.xe2x80x9d Proc. of IEEE 1992 CICC (Custom Integrated Circuits Conference), 25.2; and
[4] Yoshihiro OKAJIMA et al, xe2x80x9cDigital Delay Locked Loop and Design Technique for High-Speed Synchronous Interface.xe2x80x9d IEICE TRANS. ELECTRON., VOL. E79-C, NO. 6 JUNE 1996 pp. 798-807.
As shown in FIG. 23, the synchronous delay circuit has a basic structure which includes a set of delay circuits, namely the delay circuit 901, which is used to measure a fixed time difference, and the dummy delay circuit 905 providing a delay time corresponding to the delay time td1+td2, which is obtained by adding the delay times td1 and td2 of an input buffer 903 and clock driver 904, respectively.
In order for the dummy delay circuit 905 to make the delay time equal to the sum of the delay times td1 and td2 of the input buffer 903 and clock driver 904, respectively, there are many cases where the dummy delay circuit 905 is constructed using the input buffer dummy 905A, which comprises circuitry exactly identical with that of the input buffer, and the clock driver dummy 905B.
The delay circuit 901 and delay circuit 902 each consist of delay circuits having equal delay times.
The purpose of the delay circuit 901 is to measure a fixed period of time, and the purpose of the delay circuit 902 is to reproduce this period of time. These objects can be achieved by passing the signal through the delay circuit 901 for the measured period of time and arranging it so that the signal can be passed through the delay circuit 902 using a number of delay elements equivalent to the number of delay elements traversed by the signal in the delay circuit 901.
The following approach may be adopted to enable a signal to be passed through the delay circuit 902 using a number of delay elements equivalent to the number of delay elements traversed by the signal in the delay circuit 901: The delay circuit 901 and delay circuit 902 are divided into two types depending upon their signal propagation directions and, in order to decide the length of the delay circuit 902, the delay circuits are divided into two types depending upon whether the terminus is selected or the entire path of the circuit is selected, giving four types of delay circuits.
Specifically, if the delay circuit 901 and delay circuit 902 are divided into two types depending upon their signal propagation directions, the delay circuits 901, 902 can have the same direction, with the length of the delay circuit 902 being decided on the side of its output terminals in order to decide the number of elements in the delay circuit 902, as illustrated in FIGS. 26 and 27, or the delay circuits 901, 902 can have opposite signal propagation directions, with the length of the delay circuit 902 being decided on the side of its input terminals in order to decide the number of elements in the delay circuit 902, as depicted in FIGS. 24 and 25.
Further, in order to decide the length of the delay circuit 902, there are two types of arrangements, namely one in which the terminus is selected and one in which the entire length of the delay circuit is selected, i.e., two approaches are available, namely one in which the terminus is selected, as shown in FIGS. 24 and 27, and one in which the entire path of the delay circuit is selected, as shown in FIGS. 25 and 26.
It should be noted that FIG. 24 corresponds to the approach described in Reference [1], namely the specification of Japanese Patent Application Laid-Open (KOKAI) No. 8-237091, the application for which was filed by the present inventor.
The arrangement illustrated in FIG. 25 corresponds to the approach described in Reference [4] (IEICE TRANS. ELECTRON., VOL. E79-C, NO. 6 JUNE 1996 pp. 798-807). 
The arrangement illustrated in FIG. 26 corresponds to the approach described in Reference [2] (1996 Symp. on VLSI Circ. pp. 192-193).
The arrangement illustrated in FIG. 27 corresponds to the approach described in Reference [3] (Proc. of IEEE 1992 CICC 25.2) and Reference [4] (1996 Symp. on VLSI Circ. pp. 112-113).
For the discussion, reference will be had to the schematic views and timing charts shown in FIGS. 28 and 29 to describe an operation through which clock skew is eliminated.
FIG. 28 illustrates an instance where a synchronous delay circuit is not used. As shown at (a) in FIG. 28, an external clock 906 is utilized as an internal clock 907 upon being directed through the input buffer 903 and clock driver 904. The delay time difference between the external and internal clocks is decided by the delay time td1 of the input buffer 903 and the delay time td2 of the clock driver 904. The sum of these delay times, namely td1+td2, is the clock skew.
In order to eliminate clock skew effectively, a synchronous delay circuit utilizes the fact that a clock pulse enters at the clock period tCK. More specifically, a delay circuit providing a delay time of tCKxe2x88x92(td1+td2) is disposed between the input buffer (delay time td1) and the clock driver (delay time td2) and it is so arranged that the sum of the delay times will be equal to the clock period tCK[=td1+tCKxe2x88x92(td1+td2)+td2]. As a result, the timing of the internal clock output from the clock driver becomes equal to the timing of the external clock.
A timing chart illustrating signal timing when a illustrating signal timing when a synchronous delay circuit is actually used is illustrated in FIG. 29.
The operation of the synchronous delay circuit requires two cycles.
The first cycle is used to measure the delay time tCKxe2x88x92(td1+td2), which is dependent upon the period of the clock, and to decide the length of the delay of the delay circuit that reproduces the delay quantity tCKxe2x88x92(td1+td2).
The next cycle is used to apply the delay quantity tCKxe2x88x92(td1+td2).
In the first cycle, the dummy delay circuit 905 of the clock driver 904 and the delay circuit 901 are used to measure the delay time tCKxe2x88x92(td1+td2) dependent upon the clock cycle.
The output of the input buffer 903, namely the first pulse of two successive pulses in the external clock 906, is allowed to traverse the dummy delay circuit 905 and delay circuit 901 during one clock period tCK, which lasts until the second pulse is output from the input buffer 903. Since the delay time of the dummy delay circuit 905 is td1+td2, the time required for a pulse to propagate through the delay circuit 901 is tCKxe2x88x92(td1+td2).
The delay time of the delay circuit 902 is set so as to be equal to the time tCKxe2x88x92(td1+td2) required for a pulse to travel through the delay circuit 901.
Methods of setting the delay time of the delay circuit 902 can be classified into the four types mentioned above, and each makes it possible to attain the desired objective.
In the next cycle, the clock that emerges from the input buffer 903 passes through the delay circuit 902 of delay tCKxe2x88x92(td1+td2) and exits from the clock driver 904 to generate the internal clock 907 whose delay quantity is exactly the clock cycle tCK.
The process described above provide the internal clock 907, which is free of clock skew, in two clock cycles.
Following problems have been encountered in the course of the investigations toward the present invention.
Thus, in order to reduce external clock jitter before the external clock is used as the internal clock in the conventional clock control circuit, a feedback circuit such as a PLL is required. The feedback circuit needs a long clock period in order for the clock to stabilize and it is difficult, therefore, to attain a high-speed response. Another problem is that the synchronization characteristic is degraded by jitter.
A problem encountered with a DLL is that external clock jitter propagates intact into the internal circuitry through the delay circuit.
A synchronous delay circuit is disadvantageous in that this circuit also causes an increase in external clock jitter.
Accordingly, an object of the present invention is to provide a clock control circuit and control method for reducing jitter.
Another object of the present invention is to provide a delay-locked loop circuit, a phase synchronizing loop and a synchronous delay circuit.
According to the present invention, the foregoing objects are attained by providing a clock control circuit having a timing averaging circuit generating a signal having a time component obtained by averaging an input time difference between two signals input with a fixed time difference between them, and means (or stage) which supplies the timing averaging circuit with different pulses of a clock signal, wherein a time difference between the different pulses is subjected to internal division.
Further, the present invention provides a clock control circuit having a timing averaging circuit generating a signal having a time component obtained by averaging an input time difference between two signals input with a fixed time difference between them, and a circuit supplying the timing averaging circuit with different pulses of a clock signal, wherein a DLL circuit is equipped with a circuit internally dividing a time difference between these different pulses, the circuit having an external clock input and an internal clock input used in a phase comparison, the output of the circuit being applied to a voltage-controlled delay circuit.
Further, the present invention provides a synchronous delay circuit for controlling a clock signal, comprising: a first delay circuit chains through which a pulse or a pulse edge is caused to travel for a fixed period of time; a second delay circuit chains, to which a signal from the first delay circuit chains is input, that is capable of passing a pulse or pulse edge along a length proportional to the length along which the pulse or pulse edge traveled through the first delay circuit chains; a clock driver for outputting an internal clock from an output of the second delay circuit chains; and a timing averaging circuit, to which are input a clock signal from an input buffer and an output from an input buffer dummy having a delay time equivalent to that of the input buffer on the internal clock signal output via the clock driver, for generating and outputting a signal having a time difference obtained by internally dividing the time difference between these two signals, wherein an output of the timing averaging circuit chains is supplied to the first delay circuit chains via the dummy delay circuit.
It should be noted that an arrangement may be adopted in which travel of the clock through the first delay line is-halted for a period of time equivalent to time required for travel through input buffer dummy and clock driver.
Further aspects of the present invention are disclosed in the entire claims which constitute part of the entire disclosure and may be understood in conjunction with the disclosure of the embodiments.
Other features and advantages of the present invention will be apparent from the following description taken in conjunction with the accompanying drawings, in which like reference characters designate the same or similar parts throughout the figures thereof.